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quickly stopped falling after a few
months. The key reason for this
shift is that EDA and IP companies
don’t sell to consumers but chip
companies.
It works like this: When companies
see demand drop, they will ask
their suppliers to make fewer chips.
This scenario happened when the
automotive manufacturers cut chip
orders at the pandemic’s start. But
drastically cutting unneeded semiconductor supplies comes at a price,
as the car companies later realized
when their markets returned. It took
time to restart the chip-making
process, and hence a shortage
occurred. https://www.designnews.
com/electronics/chip-supply-shortages-float-makimotos-wave
This is generally not the case for
EDA tools and IP. One of the last
things chip companies cut during
a downturn is research and development (R&D) for new products. In
fact, it may be the one expenditure
that is increased during a technology
downturn. And that is the sweet spot
for EDA and IP.
Companies will continue to spend
— or increase spending — on-chip
development tools and IP to prepare
for the eventual demand upturn that
will come, as demonstrated time and
time again by the historical cycle.
This is why Wall Street is not seeing
much of an impact on the stocks of
Synopsys and Cadence.
John Blyler: Aside from the
cyclical economics of chip development, what complexity issues are
different now?
CHARLES SHI: The increasing complexity of designs continues to drive
the need for more powerful tools
and related IP libraries as well as
new implementation strategies such
as stacked die technologies, special
www.semiconductordigest.com
packaging, and other assembly
types. These evolving system-level
approaches have changed the traditional meaning of SoC from
“system-on-chip” to “system-ofchips.” Conveniently, the acronym is
still the same.
As further recognition of this
change, the chairman and co-CEO
of Synopsys, Aart de Geus, presented a keynote address at the 2021
Synopsys Users Group (SNUG),
which observed that Moore’s law
scaling is now blending with innovations that leverage systemic
complexity. He coined the term
SysMoore as a shorthand way to
dexsign paradigm of heterogeneous
integration.
The increasing design complexity
can be seen in the shift from 2D to
2.5D/3D integrated systems, which
require strong EDA and IP ecosystem collaboration to be successful
(see Figure 2).
JOHN BLYLER: In addition to these
economics and complexities, the
global move toward digitization must
also play a part.
CHARLES SHI: Certainly —consider this interview with Dr. Walden
Rhines that I conducted as part of
our Jun 1, 2022 “Semiconductor and
Semiconductor Equipment report:
“One overwhelming driver that
exceeds all others (for the growth
of EDA) is the entry of systems
companies into the world of integrated circuit design,” explained Dr.
Rhines. He points to systems companies entering chip design as the
#1 driver for EDA’s recent growth
accelerations. Dr. Rhines says
before systems companies came in,
people could reliably predict EDA
market size being constantly at 2%
of the semiconductor revenue. But
now, with a new set of customers
outside the traditional semiconductor industry, EDA growth, in
some sense, has decoupled from
semiconductor growth. Dr. Rhines
sees that 20-25% of the total
foundry wafers in the world today
are already bought by systemscompanies and the number may continue
to grow.
The long-term growth story for
EDA and IP is not changing in the
near term. Indeed, EDA and IP look
to outperform the rest of the industry
because companies will not slow
down R&D, especially in a semiconductor down cycle.
JOHN BLYLER: How will geopolitical
challenges like those between the US
and China affect the global EDA tool
and IP markets?
CHARLES SHI: Whatever their motivation, the Chinese continue to spend
on semiconductor self-sufficiency.
Indeed, neither the US nor China can
completely cut off ties. The industry
supply chain is too closely interwoven — at least for now.
The main reason is that you don’t
have a viable, indigenous EDA
accompany that can cover all aspects
of the chip development in China.
You always need to go Synopsis,
Cadence, or Ansys for tools and IP.
The importance of IP can not be
underestimated. IP allows designers
to kick-start their designs immediately. Plus, much of the IP is already
silicon verified, i.e., fab ready.
And there’s no point in reinventing
the wheel. Incorporating IP lets
designers focus on the features and
functionality that differentiate them
from their competitors.
For these reasons, I don’t think
there will be significant negative
EDA and IP growth in China.
JOHN BLYLER: Thank you.
Tuesday, July 12 | 13
